Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, at University of California, Santa Barbara (UCSB)
The FOSSi Foundation is proud to announce Latch-Up, a conference dedicated to free and open source silicon to be held over the weekend of Friday, March 31 to Sunday, April 2, 2023 in Santa Barbara, California, USA. (Venue details)
So save the date, register to attend, and we encourage you to submit a presentation or proposal if you have a project or idea on the topic to share!
Previous Latch-Ups: 2019 Portland · (Latch-Up 2020 was planned to take place in Cambridge, MA, but had to be cancelled.)
We encourage anybody involved in the open source semiconductor engineering space to come along and share your work or experience. Presentations slots as short as 3 minute lightning-talks and up to 30 minute talks including Q and A are available.
So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.
Presentations are submitted through the registration process and we will let you know if your presentation was accepted.
Attendance of Latch-Up is free. To help us organizing the event, you are required to register using the button below or via the EventBrite link.
Attendees who are joining us at Latch-Up on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at Latch-Up and keep the event accessible to all members of the community. Professional ticket holders are able to get their company name printed on their name badge and receive a special treat. You can buy professional tickets using the button below or via the EventBrite link.
We ask all Latch-Up participants to adhere to the the FOSSi Foundation code of conduct throughout the event.
Latch-Up is free to attend, but we aim to provide catering and the like during the event. Latch-Up is also a great way to get your company or brand in front of lots of engineers and hackers on the day, and thousands more through recordings of the event. So please get in touch if you'd like to explore sponsorship opportunities.
Latch-Up is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event, so please do email us if you would like to volunteer for during the event with setup, AV, or even just local knowledge so we can plan the weekend better.
Brief introduction of my recent project of building a RV64 processor core, which features an in-order non-blocking dual-issue pipeline, and taped out at SKY130.
RISC-V's compressed instruction (RVC) extension is intended as an add-on to the regular instruction set. Thought experiment: can a RISC-V CPU directly execute only the RVC instructions, and emulate the uncompressed instruction set in microcode? The result is Minimax: the smallest¹, fastest² RV32IC core available - with the weasel words hidden in the fine print. In this presentation, I will show how Minimax fits in with the other excellent open-source RISC-V cores already available.
Space applications present special challenges to open source technologies including high reliability and harsh environment. LeWiz Communications published several open source IP cores including Ethernet, RISC-V with network protocols and providing complete verification suites, design examples, etc. These are now targeted for space applications with specific space mission targets. This talk presents potential opportunities for space usage, the available open source technologies, challenges to space applications and uses actual applications to provide examples. Finally, it will call on the open source community to contribute to areas still lacking support for FPGA and ASIC implementations targeted for space applications.
The brain is the perfect place to look for inspiration to develop more efficient neural networks. One of the main differences with modern deep learning is that the brain encodes and processes information as spikes rather than continuous, high-precision activations. This presentation will dive into how the open-source ecosystem has been used to develop brain-inspired neuromorphic accelerators, from our development of a Python training library for spiking neural networks (snnTorch, >60,000 downloads), to compiling these next-generation deep learning models on custom ASICs submitted for tape-out in the Sky130 process. The open-source silicon movement has the potential to impact how we adopt principles from neuroscience to improving deep learning and hardware acceleration.
In response to growing application diversity, System-on-Chip (SoC) architectures have become increasingly heterogeneous, with diverse cores and accelerators, as well as non-uniform memory systems. However, existing open-source design frameworks for SoCs and NoCs (Network-on-Chips) have been unable to facilitate design exploration of heterogeneous SoC architectures with irregular NoCs. We present Constellation, a new NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures. Constellation implements a highly decoupled specification system that allows an architect to specify an exponentially large design space of irregular virtual-channel wormhole-routed NoC architectures. Additionally, Constellation provides a diverse set of systems, regression tests, and evaluation tools to provide confidence in the correctness and performance of the generated hardware. Constellation is open-sourced and integrated into the Chipyard SoC design framework, allowing full-system exploration of heterogeneous SoC architectures with irregular memory fabrics.
SiliconCompiler is a modern replacement of "make" that leverages the cloud and modern programming frameworks to lower the barrier to hardware development. (https://github.com/siliconcompiler/). The project has been successfully used in sky130 shuttle run designs and in multiple SoCs at advanced FinFET nodes. This session will give an overview of the project, followed by a set of short demos showing interesting use cases.
FireSim is an easy-to-use, open-source, FPGA-accelerated hardware simulation platform that runs on cloud and on-premises FPGAs, including AWS EC2 F1 and local machines with Xilinx Alveo boards. FireSim automatically instruments and transforms RTL designs into fast (10s-100s MHz), deterministic, and cycle-exact FPGA-based simulators that enable productive pre-silicon verification and performance validation. Users can plug in their own designs or harness the included Chipyard SoC design environment, which includes in-order and out-of-order RISC-V cores, uncore components, peripherals, and accelerators. In contrast with traditional FPGA prototyping, FireSim includes synthesizable and timing-accurate models for standard I/O interfaces like DRAM, Ethernet, UART, and others, allowing users to obtain accurate performance measurements for their pre-silicon design. FireSim also provides a large array of debugging and profiling features not available in FPGA prototypes, including assertion synthesis, print synthesis, out-of-band instruction trace and performance counter recording, Flame Graph integration, and co-simulation with software models. These features enable rapidly debugging and profiling designs trillions of cycles into simulation, without perturbing design behavior. By providing a framework to automate the management of FPGA infrastructure, FireSim lets hardware and software developers get a head-start on building software for novel hardware designs, by letting developers interact with the pre-silicon hardware design as they would a virtual machine. In effect, both hardware and software developers can work from a single source of truth: the RTL for the hardware design. FireSim also scales to simulating thousands of multi-core compute nodes, including the ability to simulate large clusters of networked designs over hundreds of FPGAs. By providing a consistent, user-friendly interface for managing simulations, FireSim enables easy scaling from small numbers of simulations hosted by on-premises FPGAs to massive simulations using hundreds of FPGAs on the cloud. This allows FireSim to remove the high capex traditionally involved in large-scale FPGA-based simulation, democratizing access to realistic pre-silicon hardware modeling of new designs. By defining standardized host platforms and providing a large amount of automation/tooling, FireSim drastically simplifies the process of building and deploying large-scale FPGA-based hardware simulations. To date, FireSim has been used in the development of commercial silicon and in published work from authors at over 20 academic and industrial institutions across various areas including computer architecture, systems, networking, circuits, security, and HPC.
We present Chipyard - an open-source integrated system-on-chip (SoC) design, simulation, and implementation environment for specialized RISC-V compute systems. Chipyard includes parameterized, composable, open-source, generator-based IP blocks that can be used across multiple stages of the hardware development flow while maintaining design intent and integration consistency. Through FPGA simulation and rapid ASIC implementation, this framework allows for continuous validation of physically realizable customized systems. Through integration with the Rocket Chip generator ecosystem, Chipyard provides a large number of easily composable and extensible open-source digital IP blocks including Linux-capable cores, accelerators, and system components. Chipyard contains mainstream energy-efficient and high-performance processor cores (Rocket, SonicBOOM, CVA6, Ibex, Sodor), domain specific accelerators (Hwacha/Gemmini/NVDLA vector/ML, SHA3/FFT/Mempress misc.), memory systems (caches, scratchpads, DRAMSim2), on-chip interconnects (Constellation) and additional peripherals to help create a fully featured SoC. Chipyard enables customization through intra-core and inter-core configuration, as well as custom extensions using the Rocket Custom Co-processor (RoCC) interface and MMIO-based devices. Chipyard also allows users to seamlessly integrate their own SystemVerilog custom IPs. Additionally, Chipyard provides software workload management tooling (FireMarshal) and toolchains for users to generate custom baremetal and Linux-based workloads for generated custom SoCs. As the SoC is co-designed for a specific use case, Chipyard enables pushing the entire SoC through automated ASIC flows (e.g. Hammer), software simulation (e.g. Verilator), FPGA prototyping flows (e.g. Vivado), and FPGA-accelerated simulation flows (e.g. FireSim). This allows the user to measure their workloads of interest in a fully automated way. Harnessing the integration with the Hammer ASIC physical design framework, users can run power-analysis simulation, go from gates to a GDSII, and more, in a minimal amount of time in both commercial and open-source process technologies (SKY130) and tooling (OpenRoad). For pre-silicon simulation and prototyping, users can use Verilator or FPGA prototyping for quick design/test cycle. For even faster continuous and simultaneous development for higher-quality verification and validation, users can use the FireSim FPGA-accelerated simulation platform for additional scale, accuracy, and debuggability. In this talk, we cover how the open-source Chipyard “one-stop shop” SoC framework enables users to create, integrate, test, and measure their own hardware designs. To date Chipyard has enabled end-to-end computer architecture research and development in over 15 academic and industrial institutions across all domains.
During this talk, I will give an introduction to systolic arrays and my work on taping out a small systolic array using only open-source tools, my work is part of the zero to ASIC community https://www.zerotoasiccourse.com/. All of the content to be presented is from the perspective of an embedded software engineer learning digital design in his free time, without previous knowledge of digital design.
Checkers are a critical part of the design verification process. With the advent of constrained-random techniques, a lot of stimulus-generation capabilities are supported by languages, methodologies, and supporting tools. Ensuring that a design behaves as per the specification is achieved using various forms of checkers. The term “checker” at times means different things to different people. With SystemVerilog 2009 standard making “checker” as a keyword in the language itself, we would like to use that for temporal checks using assertions. Verilator is a free and open-source simulator that can convert SystemVerilog code into a cycle-accurate executable model. Assertions are statements that specify properties or constraints that the design should satisfy. In this paper, we present our experience in porting some of our Checker IPs (APB, AHB, etc.) developed and used in production to Verilator. Given the SVA support is still maturing in Verilator, our team had to adapt the code to be restricted to what the tool supports. We also developed unit tests to verify these properties in Verilator. We will share our findings, potential areas to improve, etc. Our intention is to make this code base available as part of GO2UVM library.