FOSSi Dial-Up is the premier online event around Free and Open Source Silicon and EDA tools. It features selected speakers from the rapidly developing FOSSi ecosystem.
The first set of Dial-Up talks centered around the SkyWater PDK and has concluded. You can watch all recordings on YouTube.
Watch this space for announcements for the next set of talks, to start in early 2021.
If you have an interesting talk you'd like to present as part of Dial-Up, or if you'd like to help out organizing this event series, please get in touch with us at firstname.lastname@example.org.
The SkyWater Open Source Process Design Kit (PDK) is a joint project of Google and SkyWater Technology Foundry to provide a fully open source PDK.
In this event, Tim Ansell will outline the collaboration and the goals of the project. He will get into the technical details of the PDK and outline the roadmap of the project.Watch on Youtube
Unlike the wider software world, Electronic Design Automation (EDA) open-source landscape has been fragmented for a long time, requiring significant effort and knowledge in a variety of disciplines to assemble a working ASIC flow. This has changed with projects such as Qflow and OpenROAD that aim at developing open-source toolchain for digital layout generation from RTL.
OpenLane is an automated RTL to GDSII flow based on available opensource EDA tools configured/tuned for the SkyWater 130nm PDK. OpenLane main objective is to generate a clean layout from RTL designs in less than 24-hours with zero human interventions. OpenLane has been used, successfully, to tape-out a family of test chips (striVe).
For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)'s that have been completely developed using an open source process technology, open source IP and open source design automation environment.
In a collaborative effort with Google and SkyWater, efabless' team has designed and implemented the striVe SoC family using SkyWater's SKY130 130nm process, efabless' OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks - all of them are available under the Apache 2.0 license.
Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and designed SoC's stretching the limits of innovation and to serve select commercial markets.
Existing design flows and tools require excessive design costs to achieve the power, area, and performance requirements of complex system-on-chip (SoC) solutions. Consequently, the semiconductor industry needs high-level synthesis tools that provide the ability to quickly develop and accurately evaluate complex SoC solutions. These tools should provide accurate area, delay, and power estimates from high-level SoC architecture descriptions. They should also provide support for a wide variety of components including embedded memories, mixed-signal designs, custom and standard cell circuits, high-performance/low-power processors, and communication structures, such as buses and on-chip networks. In addition to being well documented, easy to use, and publicly available, the design flows should work in conjunction with industry-standard design tools.
This project will provide publicly-available high-level synthesis tools for complex SoC solutions for the SkyWater 130nm. The tools improve productivity by allowing SoC designers to quickly develop and evaluate high-performance, low-power systems. They also provide an improved understanding of area, performance, and power tradeoffs in SoC designs. The instructional materials and sample SoC architectures provided are useful for engineers, edu- cators, and students, who are new to the area of SoC design, as well. Most importantly, the tools are designed to be free and open-source software (FOSS) and integrate with tools from eFabless as well as other open-source endeavors.
OpenRAM is an open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.