45 Chips in 30 Days: Open Source ASIC at its best!
Only seven months ago, open source chips were a dream of some, and clearly impossible to others. Today we know better. In a joint effort between efabless, Google, and the SkyWater foundry, everybody got a chance to send an open source chip to fabrication. And many did!
One of the key people who made all of that happen is Mohamed Kassem, co-founder and CEO of efabless. He joined us at FOSSi Dial-Up to discuss how the “Open MPW” program went so far. (A recording of the talk is available on YouTube.)
Efabless wants to enable everyone to produce chips. As previous talks in the FOSSi Dial-Up series have shown, getting to this point requires solving a huge amount of technical, legal, and financial challenges. Taken together they made it unthinkable for hobbyists, many in academia, and even for small companies to produce their own chips. Thankfully these initial hurdles are of the past. Once the innovative power of the open source community was unleashed, many of the projects associated with the Open MPW shuttle saw an exponential rise in interest.
With interest exploding there was a lot to learn for everybody involved. Efabless, Google, and SkyWater prepared for that even before the Open MPW program was announced by producing three test chips, which were intended to validate the tooling and especially the SRAM components of the chip. An experience that paid off when they put together the Caravel Harness SoC, a “frame” with a 10mm² space in the middle for the actual chip design.
The Caravel harness consists, among other things, of a PicoRV32 RISC-V CPU core, a logic analyzer, DFT logic, and redundant memories of one kilobyte each. One memory is built out of SRAM cells, the other one out of regular flipflops. Providing such redundancy within the design, is a good practice that everyone should follow to reduce risk, as Mohamed pointed out. “Allow different ways for the chip to function.”
With the Caravel harness ready, the call to submit designs closed on November 30, 2020. The response was overwhelming. 45 designs were submitted, from which 40 were selected for the run. Even more overwhelming: 60 percent of the designs were done by first-time designers, powerfully proving the fact that chip design has truly come to the point where everyone can create their own chip.
A look at the designs that were taped out shows how diverse the motivation for producing a chip can be: open processor cores, whole Systems-on-Chip, a crypto-currency miner, a robotic app processor, an amateur satellite radio transceiver, analog, RF and embedded FPGA projects were all included.
Currently, these chip designs are being manufactured, with the 50 chips, packaged and some even on a circuit board, expected to return to their creators around the end of June. Around the same time the second fabrication round will kick off, with another one likely in December this year.
In the meantime, there is a lot to learn to better understand the fabrication process, the tooling, and how the community can come together to build open source chips. “I want to thank everyone involved in this process,” said Mohamed. “It is a continuous process that is going strong, we learn continuously from the community. It is for the first time in my life in the semiconductor industry that I have seen this level of engagement.”
To join this effort, a good starting point is the Slack channel, and the Open MPW overview page on the efabless web site.
The FOSSi Dial-Up series of talks will feature more in-depth looks at the designs that were part of the first Open MPW run, as well as other interesting topics around free and open source silicon. Head over to the Dial-Up web site for an up-to-date list of talks, and subscribe to the monthly newsletter of the FOSSi Foundation, El Correo Libre.