The Google Summer of Code (GSoC) has started and we are happy to announce that we have seven students working for projects related to FOSSi Foundation:
Analysis of WARP-V on FireSim with RocketChip, Alaa Salman
The WARP-V RISC-V core generator was developed in 2018 as a configurable, adaptable open-source RISC-V CPU core generator, taking advantage of advanced digital design features of TL-Verilog. It can be configured as a low-power, slow-clock, single stage pipeline, a high-frequency seven-stage pipeline, or anywhere in between. You can even swap out the RISC-V ISA for a completely different ISA altogether.
Alaa will to analyze the architectural performance of WARP-V using an open source tool ‘FireSim’ and RocketChip. FireSim is an open-source cycle-accurate FPGA-accelerated full-system hardware simulation platform that runs on cloud FPGAs (Amazon EC2 F1). FireSim is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley. Berkeley also releases a Chisel generator called “Rocket-Chip”. RocketChip generator is a Scala program that invokes the Chisel compiler in order to emit RTL describing a complete SoC.
Continuous Integration for Hardware Projects on LibreCores CI, Nancy Chauhan
Librecores provides a platform to share projects and ideas, in the area of free and open source digital hardware design. Librecores CI is an approach/service to provide continuous integration to hardware projects hosted on Librecores to improve user experience and reliability. This project aims to provide automation service for some hardware projects that have a constantly evolving code. Jenkins, the automation server will be used to achieve the goals of the project.
Enhancing JuxtaPiton with X86 Support, Kunal Gulati
JuxtaPiton is an architecture being developed at Princeton’s Parallel Group for heterogeneous ISA research. For this project, Kunal will replace the existing picorv32 core with the open-source ao486 core to have x86 ISA support along with the OpenSPARC T1’s SPARC V9. This kind of a heterogeneous system enables reuse of a lot of legacy x86 code. We also try to interface the L1 cache level of ao486 with the L1.5 cache subsystem of OpenPiton. This allows us to harness Piton’s P-Mesh subsystem which maintains cache coherency across both the cores.
This project aims to develop user interactivity on the LibreCores community hub through a full-fledged notification system and a platform to record user feedback. The notification system will be used to notify users associated with events and by the community to convey information to their audience i.e. the users, and the user feedback system will be used to determine the project quality/popularity amongst the developers.
FPGA-Accelerated Web Applications, Ákos Hadnagy
Building hardware requires access to costly tools and hardware, furthermore complexity in hardware design remains a deterrent force. FPGAs in the cloud solved the high upfront cost of the hardware, and some aspects of tool availability, but not the complexity and scale yet. Moreover, reuse of the already existing IPs is extremely difficult.
For this Summer of Code project, an extension to the FPGA-Webserver project is proposed to provide an end-to-end solution for accelerating web applications and developing hardware using cloud FPGAs.
A ready-to-use environment like this could potentially accelerate compute-intensive tasks in web applications and could appear in online HW design tools as backend.
LLVM Code Generation for RISC-V Open Source GPU, Reshabh Sharma
Bespoke Silicon group at University of Washington is working on the second version of their open source RISC-V manycore processor. They are also working on a CUDA-light programming environment using LLVM. In this project Reshabh plan to extend RV32 LLVM backend incorporating new hardware features.
Microarchitectural enhancement of Ariane, Zach Zheng
This project is to add Microarchitectural enhancement of Ariane that is a popular open-source CPU core implementing the RISC-V ISA (instruction set architecture). Currently, the processor is single-issue, meaning that the processor can only issue one instruction per clock cycle. That is a huge performance bottleneck since most functional units in the processor will stay idle when it does not have any instructions to proceed. In this project, I will implement super-scalar issue logic which allows Ariane to issue two (or more) instructions in the same clock cycle so that the overall performance will be greatly improved.
The coding of the projects has just started and we look forward to an exciting summer of code and great output. We will keep you posted about the progress of our students.